Hex D-type flip-flop with reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap

文件：101.56 Kbytes 页数：13 Pages

PHI

飞利浦

Hex D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requ

文件：255.38 Kbytes 页数：14 Pages

NEXPERIA

安世

Hex D-type flip-flop with reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap

文件：101.56 Kbytes 页数：13 Pages

PHI

飞利浦

Hex D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold

文件：252.1 Kbytes 页数：14 Pages

NEXPERIA

安世

Hex D-type flip-flop with reset; positive-edge trigger

文件：730.95 Kbytes 页数：16 Pages

NEXPERIA

安世

Hex D-type flip-flop with reset; positive-edge trigger

The 74HC174; 74HCT174 are hex positive edge -triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR ) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIG • Input levels:• For 74HC174: CMOS level\n• For 74HCT174: TTL level\n\n• Six edge-triggered D-type flip-flops\n• Asynchronous master reset\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V.\n\n• Multiple package options\n• Sp;

Nexperia

安世

74HC CMOS logic IC series

Function：Hex D-Type Flip-Flop with Clear\nNumber of Circuits：6\nRoHS Compatible Product(s) (#)：Available\nAssembly bases：日本 Power Dissipation PD 500 mW ;

Toshiba

东芝

Package：16-SOIC（0.154"，3.90mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 6BIT 16SOIC

Toshiba Semiconductor and Storage

Hex D-type flip-flop with reset; positive-edge trigger

The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LO • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Input levels:• For 74HC174-Q100: CMOS level\n• For 74HCT174-Q100: TTL level\n\n• Six edge-triggered D-type flip-flops\n• Asynchronous master reset\n• Complies wit;

Nexperia

安世

Package：16-SOIC（0.154"，3.90mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE SNGL 6BIT 16SO

Nexperia USA Inc.