Presettable synchronous 4-bit binary counter; asynchronous reset

The 74HC161-Q100 is a synchronous preset table binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at t • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC161-Q100: CMOS level\n\n• Synchronous counting and loading\n• 2 count enable inputs for n-bit cascading\n• Asynchronous reset\n• Positive-edge triggered clock\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A excee;

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Presettable synchronous 4-bit binary counter; asynchronous reset

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Package：16-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 计数器，除法器 描述：IC SYNC 4BIT BINARY COUNT

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TI
SOP/DIP

TI

德州仪器

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FM/富满
SOP-14

FM/富满

上传：深圳广友电子有限公司