Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

文件：124.81 Kbytes 页数：17 Pages

PHI

PHI

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

文件：295.88 Kbytes 页数：25 Pages

PHI

PHI

Dual retriggerable monostable multivibrator with reset

General description The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output pulse width co

文件：155.34 Kbytes 页数：24 Pages

恩XP

High Speed CMOS Logic

Features Triggerable via positive or negative edge Re-triggerable for very long pulses up to 100% duty factor Direct reset terminates output Schmitt trigger action for A & B inputs Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and

文件：451.21 Kbytes 页数：7 Pages

SS

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123; 74HCT123 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the edge trig

文件：322.18 Kbytes 页数：20 Pages

NEXPERIA

安世

High Speed CMOS Logic

Features Triggerable via positive or negative edge Re-triggerable for very long pulses up to 100% duty factor Direct reset terminates output Schmitt trigger action for A & B inputs Output Drive Capability: 10 LSTTL Loads Low Input Current: 1μA Outputs directly interface CMOS, NMOS and

文件：451.21 Kbytes 页数：7 Pages

SS

Dual retriggerable monostable multivibrator with reset

General description The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output pulse width co

文件：155.34 Kbytes 页数：24 Pages

恩XP

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

文件：295.88 Kbytes 页数：25 Pages

PHI

PHI

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123; 74HCT123 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the edge trig

文件：322.18 Kbytes 页数：20 Pages

NEXPERIA

安世

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123-Q100; 74HCT123-Q100 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the

文件：315.15 Kbytes 页数：20 Pages

NEXPERIA

安世