Quad 2-input NAND gate

General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC00; 74HCT00 provides a quad 2-input NAND function. Features and benefits  Input levels:  For 74HC00: CMO

文件：129.81 Kbytes 页数：16 Pages

恩XP

Quad 2-input NAND gate

1. General description The 74HC00-Q100; 74HCT00-Q100 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standar

文件：240.42 Kbytes 页数：12 Pages

NEXPERIA

安世

Quad 2-input NAND gate

1. General description The 74HC00-Q100; 74HCT00-Q100 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standar

文件：240.41 Kbytes 页数：12 Pages

NEXPERIA

安世

Quad 2-input NAND gate

1. General description The 74HC00; 74HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • Wide supply voltage range from 2.0 to 6.0 V • CMOS low power dis

文件：239.87 Kbytes 页数：12 Pages

NEXPERIA

安世

Quad 2-input NAND gate

General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC00; 74HCT00 provides a quad 2-input NAND function. Features and benefits  Input levels:  For 74HC00: CMO

文件：129.81 Kbytes 页数：16 Pages

恩XP

丝印：14；Package：SOT108-1；Quad 2-input NAND gate

DESCRIPTION The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC00/74HCT00 provide the 2-input NAND function. FEATURES • Complies with JEDEC standard no. 8-1A •

文件：28.03 Kbytes 页数：5 Pages

PHI

PHI

丝印：74HC00D；Package：SOIC14；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Quad 2-Input NAND Gate General The 74HC00D is a high speed CMOS 2-INPUT NAND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The internal circuit is

文件：171.47 Kbytes 页数：8 Pages

TOSHIBA

东芝

Quad 2-input NAND gate

General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC00; 74HCT00 provides a quad 2-input NAND function. Features and benefits ■ Input levels: ◆ For 74HC00: CM

文件：173.63 Kbytes 页数：15 Pages

恩XP

Quad 2-input NAND gate

General description The 74HC00; 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC00; 74HCT00 provides a quad 2-input NAND function. Features and benefits ■ Input levels: ◆ For 74HC00: CM

文件：130.33 Kbytes 页数：16 Pages

恩XP

丝印：14；Package：SOT337-1；Quad 2-input NAND gate

DESCRIPTION The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC00/74HCT00 provide the 2-input NAND function. FEATURES • Complies with JEDEC standard no. 8-1A •

文件：28.03 Kbytes 页数：5 Pages

PHI

PHI