8-bit bidirectional universal shift register

DESCRIPTION The 74F166 is a high speed 8–bit shift register that has fully synchronous serial parallel data entry selected by an active low parallel enable (PE) input. When the PE is low one setup time before the low–to–high clock transition, parallel data is entered into the register. FEA

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PHI

4-bit up/down binary synchronous counter

DESCRIPTION The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down counter featuring an internal carry look-ahead for applications in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with

文件：116.33 Kbytes 页数：12 Pages

PHI

PHI

4-Stage Synchronous Bidirectional Counter

General Description The 74F169 is a fully synchronous 4-stage up/down counter. The 74F169 is a modulo-16 binary counter. Features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in

文件：89.47 Kbytes 页数：8 Pages

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4-Stage Synchronous Bidirectional Counter

General Description The 74F169 is a fully synchronous 4-stage up/down counter. The 74F169 is a modulo-16 binary counter. Features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in

文件：89.47 Kbytes 页数：8 Pages

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仙童半导体

4-Stage Synchronous Bidirectional Counter

General Description The 74F169 is a fully synchronous 4-stage up/down counter. The 74F169 is a modulo-16 binary counter. Features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in

文件：89.47 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体

4-Stage Synchronous Bidirectional Counter

General Description The 74F169 is a fully synchronous 4-stage up/down counter. The 74F169 is a modulo-16 binary counter. Features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in

文件：89.47 Kbytes 页数：8 Pages

FAIRCHILD

仙童半导体

Quad D-type flip-flop 3-State

DESCRIPTION The 74F173 is a high speed 4–bit parallel load register with clock enable control, 3–state buffered outputs, and master reset (MR). When the two clock enable (E0 and E1) inputs are low, the data on the D inputs is loaded into the register simultaneously with low–to–high clock (CP) tra

文件：88.51 Kbytes 页数：10 Pages

PHI

PHI

Hex D flip-flops

DESCRIPTION The 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup ti

文件：75.93 Kbytes 页数：8 Pages

PHI

PHI

Hex D-Type Flip-Flop with Master Reset

General Description The 74F174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear

文件：57.44 Kbytes 页数：6 Pages

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Hex D-Type Flip-Flop with Master Reset

General Description The 74F174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear

文件：57.44 Kbytes 页数：6 Pages

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