8-input priority encoder

DESCRIPTION The 74F148 8-input priority encoder accepts data from eight active-Low inputs and provides a binary representation on the three active-Low outputs. A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is

文件：85.68 Kbytes 页数：10 Pages

PHI

PHI

8-Line to 3-Line Priority Encoder

General Description The F148 provides three bits of binary coded output repre senting the position of the highest order active input, along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide priority encoding over many bits.

文件：61.62 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

8-input priority encoder

DESCRIPTION The 74F148 8-input priority encoder accepts data from eight active-Low inputs and provides a binary representation on the three active-Low outputs. A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is

文件：85.68 Kbytes 页数：10 Pages

PHI

PHI

8-Line to 3-Line Priority Encoder

General Description The F148 provides three bits of binary coded output repre senting the position of the highest order active input, along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide priority encoding over many bits.

文件：61.62 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

8-Line to 3-Line Priority Encoder

General Description The F148 provides three bits of binary coded output repre senting the position of the highest order active input, along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide priority encoding over many bits.

文件：61.62 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

8-Line to 3-Line Priority Encoder

General Description The F148 provides three bits of binary coded output repre senting the position of the highest order active input, along with an output indicating the presence of any active input. It is easily expanded via input and output enables to provide priority encoding over many bits.

文件：61.62 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Hex Inverter Schmitt Trigger

General Description The 74F14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin

文件：50 Kbytes 页数：4 Pages

FAIRCHILD

仙童半导体

Hex Inverter Schmitt Trigger

General Description The 74F14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin

文件：50 Kbytes 页数：4 Pages

FAIRCHILD

仙童半导体

Hex Inverter Schmitt Trigger

General Description The 74F14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin

文件：68.9 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Hex Inverter Schmitt Trigger

General Description The 74F14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin

文件：50 Kbytes 页数：4 Pages

FAIRCHILD

仙童半导体