丝印：pT；Package：SOT1116；Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition

文件：279.64 Kbytes 页数：19 Pages

NEXPERIA

安世

Low-power dual D-type flip-flop; positive-edge trigger

The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.\ • Wide supply voltage range from 0.8 V to 3.6 V\n• High noise immunity\n• Complies with JEDEC standards:• JESD8-12 (0.8 V to 1.3 V)\n• JESD8-11 (0.9 V to 1.65 V)\n• JESD8-7 (1.2 V to 1.95 V)\n• JESD8-5 (1.8 V to 2.7 V)\n• JESD8-B (2.7 V to 3.6 V)\n\n• ESD protection:• HBM JESD22-A114F Class 3A excee;

Nexperia

安世

Package：8-XFDFN；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 8XSON

Nexperia USA Inc.

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition

文件：279.64 Kbytes 页数：19 Pages

NEXPERIA

安世

Low-power dual D-type flip-flop; positive-edge trigger

文件：94.62 Kbytes 页数：18 Pages

PHI

PHI