丝印：pP；Package：SOT1116；Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

文件：279.06 Kbytes 页数：19 Pages

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Low-power dual D-type flip-flop; positive-edge trigger

The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable o • Wide supply voltage range from 0.8 V to 3.6 V\n• Complies with JEDEC standards:• JESD8-12 (0.8 V to 1.3 V)\n• JESD8-7 (1.2 V to 1.95 V)\n• JESD8-B (2.7 V to 3.6 V)\n• ESD protection:• HBM JESD22-A114F Class 3A exceeds 5000 V\n• CDM JESD22-C101E exceeds 1000 V\n• Low static power consumption; ICC =;

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Package：8-XFDFN；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：标准 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 8XSON

Nexperia USA Inc.

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

文件：279.06 Kbytes 页数：19 Pages

NEXPERIA

安世

Low-power dual D-type flip-flop; positive-edge trigger

1. General description The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock

文件：279.06 Kbytes 页数：19 Pages

NEXPERIA

安世