丝印：aE；Package：SOT1116；Low-power dual 2-input NAND Schmitt trigger

1. General description The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IO

文件：309.84 Kbytes 页数：21 Pages

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Low-power dual 2-input NAND Schmitt trigger

The 74AUP2G132 provides the dual 2-input NAND Schmitt trigger function which accepts standard input signals. They can transform slowly changing input signals into sharply defined, jitter-free output signals.\n This device ensures a very low static and dynamic power consumption across the entire V • Wide supply voltage range from 0.8 V to 3.6 V\n• ESD protection:• HBM JESD22-A114F Class 3A exceeds 5000 V\n• CDM JESD22-C101E exceeds 1000 V\n• Low static power consumption; ICC = 0.9 μA (maximum)\n• Inputs accept voltages up to 3.6 V\n• IOFF circuitry provides partial Power-down mode operation\n;

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Package：8-XFDFN；包装：卷带（TR） 类别：集成电路（IC） 门和反相器 描述：IC GATE NAND 2CH 2IN 8XSON

Nexperia USA Inc.

Low-power dual 2-input NAND Schmitt trigger

1. General description The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IO

文件：309.84 Kbytes 页数：21 Pages

NEXPERIA

安世

Low-power dual 2-input NAND Schmitt trigger

1. General description The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IO

文件：309.84 Kbytes 页数：21 Pages

NEXPERIA

安世