18-bit bus-interface D-type flip-flop with reset and enable with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positiv

文件：103.74 Kbytes 页数：14 Pages

PHI

PHI

18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state

1 General description The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity. The 74ALVT162823 has two 9-bit wide buffered registers w

文件：226.83 Kbytes 页数：18 Pages

NEXPERIA

安世

18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state

1 General description The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity. The 74ALVT162823 has two 9-bit wide buffered registers w

文件：226.83 Kbytes 页数：18 Pages

NEXPERIA

安世

18-bit bus-interface D-type flip-flop with reset and enable with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positiv

文件：103.74 Kbytes 页数：14 Pages

PHI

PHI

18-bit bus-interface D-type flip-flop with reset and enable with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positiv

文件：103.74 Kbytes 页数：14 Pages

PHI

PHI

18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state

The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity.\n The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) • Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops\n• 5 V I/O compatible\n• Ideal where high speed, light loading or increased fan-in are required with MOS microprocessors\n• Bus hold data inputs eliminate the need for external pull-up resistors to hold unused;

Nexperia

安世

18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm terminationresistors; 3-state

The 74ALVT162823 is an 18-bit positive-edge triggered D-type flip-flop with 30 Ω termination resistors, 3-state outputs reset and enable.\n The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output e

Nexperia

安世

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 9BIT 56TSSOP

Nexperia USA Inc.

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 9BIT 56TSSOP

Nexperia USA Inc.

Package：56-BSSOP（0.295"，7.50mm 宽）；包装：管件 功能：主复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 9BIT 56SSOP

Nexperia USA Inc.