18-bit universal bus transceiver 3-State

DESCRIPTION The 74ALVCH16600 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. F

文件：88.75 Kbytes 页数：14 Pages

PHI

PHI

18-bit universal bus transceiver; 3-state

1 General description The 74ALVCH16600 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CP

文件：210.57 Kbytes 页数：17 Pages

NEXPERIA

安世

18-bit universal bus transceiver; 3-state

1 General description The 74ALVCH16600 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CP

文件：210.57 Kbytes 页数：17 Pages

NEXPERIA

安世

18-bit universal bus transceiver 3-State

DESCRIPTION The 74ALVCH16600 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. F

文件：88.75 Kbytes 页数：14 Pages

PHI

PHI

18-bit universal bus transceiver (3-State)

文件：93.05 Kbytes 页数：14 Pages

PHI

PHI

18-bit universal bus transceiver; 3-state

The 74ALVCH16600 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data • CMOS low power consumption\n• MultiByte flow-through standard pin-out architecture\n• Low inductance multiple VCC and GND pins for minimum noise and ground bounce\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• Bus hold on data inputs\n• Output drive capability 50 Ω transmission lines at 8;

Nexperia

安世

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 通用总线功能 描述：IC UNIV BUS TXRX 18BIT 56TSSOP

TI

德州仪器

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 通用总线功能 描述：IC UNIV BUS TXRX 18BIT 56TSSOP

TI

德州仪器

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：管件 类别：集成电路（IC） 通用总线功能 描述：IC UNIV BUS TXRX 18BIT 56TSSOP

Nexperia USA Inc.