16-bit D-type registered transceiver; 3-state

DESCRIPTION The 74ALVCH16543 is a dual octal registered transceiver. FEATURES • In accordance with JEDEC standard no 8-1A • CMOS low power consumption • Direct interface with TTL levels • MULTIBYTE flow-through pin-out architecture • 16-bit transceiver with D-type latch • Combines 16

文件：89.86 Kbytes 页数：20 Pages

PHI

PHI

16-bit D-type registered transceiver; 3-state

1 General description The 74ALVCH16543 is a dual octal registered transceiver. Each section contains two sets of D-type latches for temporary storage of the data flow in either direction. Separate latch enable (nLEAB, nLEBA) and output enable (nOEAB, nOEBA) inputs are provided for each registe

文件：204.93 Kbytes 页数：17 Pages

NEXPERIA

安世

16-bit D-type registered transceiver; 3-state

1 General description The 74ALVCH16543 is a dual octal registered transceiver. Each section contains two sets of D-type latches for temporary storage of the data flow in either direction. Separate latch enable (nLEAB, nLEBA) and output enable (nOEAB, nOEBA) inputs are provided for each registe

文件：204.93 Kbytes 页数：17 Pages

NEXPERIA

安世

16-bit D-type registered transceiver; 3-state

DESCRIPTION The 74ALVCH16543 is a dual octal registered transceiver. FEATURES • In accordance with JEDEC standard no 8-1A • CMOS low power consumption • Direct interface with TTL levels • MULTIBYTE flow-through pin-out architecture • 16-bit transceiver with D-type latch • Combines 16

文件：89.86 Kbytes 页数：20 Pages

PHI

PHI

16-bit D-type registered transceiver; 3-state

文件：103.85 Kbytes 页数：20 Pages

PHI

PHI

16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

文件：356.96 Kbytes 页数：16 Pages

TI

德州仪器

16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

文件：356.96 Kbytes 页数：16 Pages

TI

德州仪器

16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

文件：356.96 Kbytes 页数：16 Pages

TI

德州仪器

16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

文件：356.96 Kbytes 页数：16 Pages

TI

德州仪器

16-bit D-type registered transceiver; 3-state

The 74ALVCH16543 is a dual octal registered transceiver. Each section contains two sets of D-type latches for temporary storage of the data flow in either direction.\n Separate latch enable (nLEAB, nLEBA) and output enable (nOEAB, nOEBA) inputs are provided for each register to permit independent • CMOS low power consumption\n• Direct interface with TTL levels\n• MULTIBYTE flow-through standard pin-out architecture\n• Back-to-back registers for storage\n• Output drive capability 50 Ω transmission lines at 85 °C\n• All data inputs have bus hold\n• Low inductance multiple VCC and GND pins for ;

Nexperia

安世