18-bit registered driver with inverted register enable 3-State

DESCRIPTION The 74ALVC16834A is an 18-bit registered driver. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • MULTIBYTETM flow-through stan

文件：121.81 Kbytes 页数：12 Pages

PHI

PHI

18-bit registered driver with inverted register enable; 3-state

1 General description The 74ALVC16834A is an 18-bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is l

文件：200.71 Kbytes 页数：15 Pages

NEXPERIA

安世

18-bit registered driver with inverted register enable; 3-state

1 General description The 74ALVC16834A is an 18-bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is l

文件：200.71 Kbytes 页数：15 Pages

NEXPERIA

安世

18-bit registered driver with inverted register enable 3-State

DESCRIPTION The 74ALVC16834A is an 18-bit registered driver. FEATURES • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • MULTIBYTETM flow-through stan

文件：121.81 Kbytes 页数：12 Pages

PHI

PHI

18-bit registered driver with inverted register enable (3‑state)

The 74ALVC16834A is an 18-bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP).\n When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to H • Wide supply voltage range of 1.2 V to 3.6 V\n• Complies with JEDEC standard no. 8-1A\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Current drive ±24 mA at 3.0 V\n• MULTIBYTE™ flow-through standard pin-out architecture\n• Low inductance multiple VCC and GND pins for minimum n;

Nexperia

安世

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：管件 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUF NON-INVERT 3.6V 56TSSOP

Nexperia USA Inc.

Package：56-TFSOP（0.240"，6.10mm 宽）；包装：管件 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUF NON-INVERT 3.6V 56TSSOP

Nexperia USA Inc.