Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26??Series Resistors in Outputs

General Description The ALVC162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. The ALVC162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications suc

文件：89.92 Kbytes 页数：7 Pages

FAIRCHILD

仙童半导体

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series Resistors in Outputs

ONSEMI

安森美半导体

18-bit registered driver with 30 Ω termination resistors; 3-state

1 General description The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW

文件：201.1 Kbytes 页数：15 Pages

NEXPERIA

安世

18-bit registered driver with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tran

文件：94.29 Kbytes 页数：12 Pages

PHI

PHI

18-bit registered driver with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tran

文件：94.29 Kbytes 页数：12 Pages

PHI

PHI

18-bit registered driver with 30 Ω termination resistors; 3-state

1 General description The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW

文件：201.1 Kbytes 页数：15 Pages

NEXPERIA

安世

丝印：ALVC162835；Package：TSSOP(DGG)；18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Max tpd of 2 ns at 3.3 V ±12-mA Output Drive at 3.3 V Ideal for Use in PC100 Register DIMM, Revision 1.1 Output Port Has Equivalent 26-W Series Resistors, So No External Resistors Are Required Latch-U

文件：566.51 Kbytes 页数：14 Pages

TI

德州仪器

丝印：ALVC162835；Package：TSSOP(DGG)；18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Max tpd of 2 ns at 3.3 V ±12-mA Output Drive at 3.3 V Ideal for Use in PC100 Register DIMM, Revision 1.1 Output Port Has Equivalent 26-W Series Resistors, So No External Resistors Are Required Latch-U

文件：566.51 Kbytes 页数：14 Pages

TI

德州仪器

丝印：ALVC162835；Package：TSSOP；18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 V to 3.6 V · Max tpd of 2 ns at 3.3 V · ±12-mA Output Drive at 3.3 V · Ideal for Use in PC100 Register DIMM, Revision 1.1 · Output Port Has Equivalent 26-W Series Resistors, So No External Resistors Are Requi

文件：1.0702 Mbytes 页数：14 Pages

TI

德州仪器

18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES · Member of the Texas Instruments Widebus™ Family · Operates From 1.65 V to 3.6 V · Max tpd of 2 ns at 3.3 V · ±12-mA Output Drive at 3.3 V · Ideal for Use in PC100 Register DIMM, Revision 1.1 · Output Port Has Equivalent 26-W Series Resistors, So No External Resistors Are Requi

文件：1.06968 Mbytes 页数：14 Pages

TI

德州仪器