Quad 2-input NOR gate

1. General description The 74ALVC02 is a quad 2-input NOR gate. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. 2. Features and benefits • Wide supply voltage range from 1.65 V to 3.6 V • 3.6 V tolerant inputs/outputs • CMOS low power con

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Hex inverter

1. General description The 74ALVC04 is a hex inverter. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Schmitt-trigger action

文件：232.98 Kbytes 页数：13 Pages

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Hex inverter

1. General description The 74ALVC04 is a hex inverter. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Schmitt-trigger action

文件：232.98 Kbytes 页数：13 Pages

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Hex inverter

1. General description The 74ALVC04 is a hex inverter. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Schmitt-trigger action

文件：232.98 Kbytes 页数：13 Pages

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Hex inverter

1. General description The 74ALVC04 is a hex inverter. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Schmitt-trigger action

文件：232.98 Kbytes 页数：13 Pages

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Quad 2-input AND gate

1. General description The 74ALVC08 is a quad 2-input AND gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Schmitt-trigge

文件：234.11 Kbytes 页数：13 Pages

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Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs

General Description The ALVC08 contains four 2-input AND gates. This product is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V The ALVC08 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power d

文件：89.69 Kbytes 页数：5 Pages

FAIRCHILD

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Quad 2-input AND gate

DESCRIPTION The 74ALVC08 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. The 74ALVC08 provides the 2-input AND fun

文件：87.3 Kbytes 页数：16 Pages

PHI

PHI

Quad 2-input AND gate

DESCRIPTION The 74ALVC08 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. The 74ALVC08 provides the 2-input AND fun

文件：87.3 Kbytes 页数：16 Pages

PHI

PHI

Quad 2-input AND gate

1. General description The 74ALVC08 is a quad 2-input AND gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Schmitt-trigge

文件：234.11 Kbytes 页数：13 Pages

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