Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs

General Description The ALVC132 contains four 2-input NAND gates with Schmitt Trigger Inputs. The pin configuration and function are the same as the ALVC00 except the inputs have hysteresis between the positive-going and negative-going input thresholds. This hysteresis is useful for transforming

文件：94.9 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs

General Description The ALVC132 contains four 2-input NAND gates with Schmitt Trigger Inputs. The pin configuration and function are the same as the ALVC00 except the inputs have hysteresis between the positive-going and negative-going input thresholds. This hysteresis is useful for transforming

文件：94.9 Kbytes 页数：5 Pages

FAIRCHILD

仙童半导体

Hex inverting Schmitt trigger

General description The 74ALVC14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals int

文件：92.06 Kbytes 页数：16 Pages

PHI

PHI

Hex inverting Schmitt trigger

1. General description The 74ALVC14 is a hex inverter with Schmitt-trigger inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered do

文件：254.63 Kbytes 页数：16 Pages

NEXPERIA

安世

Hex inverting Schmitt trigger

1. General description The 74ALVC14 is a hex inverter with Schmitt-trigger inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered do

文件：254.63 Kbytes 页数：16 Pages

NEXPERIA

安世

Hex inverting Schmitt trigger

General description The 74ALVC14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals int

文件：92.06 Kbytes 页数：16 Pages

PHI

PHI

Hex inverting Schmitt trigger

1. General description The 74ALVC14 is a hex inverter with Schmitt-trigger inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered do

文件：254.63 Kbytes 页数：16 Pages

NEXPERIA

安世

Hex inverting Schmitt trigger

General description The 74ALVC14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals int

文件：92.06 Kbytes 页数：16 Pages

PHI

PHI

Hex inverting Schmitt trigger

General description The 74ALVC14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals int

文件：92.06 Kbytes 页数：16 Pages

PHI

PHI

Hex inverting Schmitt trigger

1. General description The 74ALVC14 is a hex inverter with Schmitt-trigger inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered do

文件：254.63 Kbytes 页数：16 Pages

NEXPERIA

安世