Hex D flip-flop

DESCRIPTION The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set

文件：97.78 Kbytes 页数：8 Pages

PHI

PHI

Advanced Low Power Schottky Logic

Features High speed – 2ns (Min) propagation delay Direct drop-in replacement for obsolete components in long term programs.

文件：715.21 Kbytes 页数：5 Pages

SS

Advanced Low Power Schottky Logic

Features High speed – 2ns (Min) propagation delay Direct drop-in replacement for obsolete components in long term programs.

文件：769.5 Kbytes 页数：5 Pages

SS

Advanced Low Power Schottky Logic

Features High speed – 2ns (Min) propagation delay Direct drop-in replacement for obsolete components in long term programs.

文件：769.5 Kbytes 页数：5 Pages

SS

Hex D flip-flop

DESCRIPTION The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set

文件：97.78 Kbytes 页数：8 Pages

PHI

PHI

Hex D flip-flop

DESCRIPTION The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set

文件：97.78 Kbytes 页数：8 Pages

PHI

PHI

Quad D flip-flop

DESCRIPTION The 74ALS175 is a quad, edge-triggered D-type flip-flops with individual D inputs and both Q and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D inpu

文件：99.91 Kbytes 页数：8 Pages

PHI

PHI

Quad D flip-flop

DESCRIPTION The 74ALS175 is a quad, edge-triggered D-type flip-flops with individual D inputs and both Q and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D inpu

文件：99.91 Kbytes 页数：8 Pages

PHI

PHI

Quad D flip-flop

DESCRIPTION The 74ALS175 is a quad, edge-triggered D-type flip-flops with individual D inputs and both Q and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D inpu

文件：99.91 Kbytes 页数：8 Pages

PHI

PHI