74ALS174D中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.

All Q outputs will be forced Low independent of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where true outputs only are required, and the clock and master reset are common to all storage elements.

FEATURES

• Four edge-triggered D flip-flops

• Buffered common clock

• Buffered asynchronous master reset