Quad D flip-flop

DESCRIPTION The 74ALS175 is a quad, edge-triggered D-type flip-flops with individual D inputs and both Q and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D inpu

文件：99.91 Kbytes 页数：8 Pages

PHI

飞利浦

Hex/Quad D-Type Flip-Flops with Clear

文件：331.27 Kbytes 页数：9 Pages

Fairchild

仙童半导体

Hex/Quad D-Type Flip-Flops with Clear

General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and the quad (DM74ALS175) version features complementary outputs from each flip-flop. Information at the D inputs meeting the setup time

文件：73.3 Kbytes 页数：7 Pages

Fairchild

仙童半导体

Hex/Quad D-Type Flip-Flops with Clear

文件：331.27 Kbytes 页数：9 Pages

Fairchild

仙童半导体