Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

文件：93.6 Kbytes 页数：9 Pages

PHI

PHI

Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

文件：93.6 Kbytes 页数：9 Pages

PHI

PHI

Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

文件：93.6 Kbytes 页数：9 Pages

PHI

PHI

Dual J-K Positive-Edge-Triggered Flip-Flop

General Description The DM74ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs. Features ■ Switching specifications at 50 pF ■ Switching specifications guaranteed over full temperature

文件：55.43 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual J-K Positive-Edge-Triggered Flip-Flop

General Description The DM74ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs. Features ■ Switching specifications at 50 pF ■ Switching specifications guaranteed over full temperature

文件：55.43 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体

Dual J-K Positive-Edge-Triggered Flip-Flop

General Description The DM74ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs. Features ■ Switching specifications at 50 pF ■ Switching specifications guaranteed over full temperature

文件：55.43 Kbytes 页数：6 Pages

FAIRCHILD

仙童半导体