Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

文件：93.6 Kbytes 页数：9 Pages

PHI

PHI

Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

文件：93.6 Kbytes 页数：9 Pages

PHI

PHI

Dual J-K positive edge-triggered flip-flop with set and reset

DESCRIPTION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K ar

文件：93.6 Kbytes 页数：9 Pages

PHI

PHI

Triple 3-Input NAND gate

Triple 3-Input NAND gate

文件：86.1 Kbytes 页数：7 Pages

PHI

PHI

Triple 3-Input NAND gate

Triple 3-Input NAND gate

文件：86.1 Kbytes 页数：7 Pages

PHI

PHI

Triple 3-Input NAND gate

Triple 3-Input NAND gate

文件：86.1 Kbytes 页数：7 Pages

PHI

PHI

Hex Inverting Drivers with Open Collector Outputs

文件：182.33 Kbytes 页数：2 Pages

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