Octal D-type transparent latch; 3-state

1. General description The 74AHC573-Q100; 74AHCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch

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Octal D-type transparant latch 3-state

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Octal D-type transparent latch; 3-state

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Octal D-type transparent latch; 3-state

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飞利浦

Octal D-type transparant latch 3-state

文件：732.68 Kbytes 页数：19 Pages

NEXPERIA

安世

Octal D-type transparent latch; 3-state

文件：91.69 Kbytes 页数：20 Pages

PHI

飞利浦

Octal D-type transparent latch; 3-state

文件：138.66 Kbytes 页数：23 Pages

PHI

飞利浦

Octal D-type transparant latch 3-state

文件：732.68 Kbytes 页数：19 Pages

NEXPERIA

安世

Octal D-type transparant latch; 3-state

The 74AHC573-Q100; 74AHCT573-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.\n The 74AHC573-Q100; 74AHCT573-Q100 consists of eight D-type transparent latches featuring separate D-type inp • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have a Schmitt trigger action\n• Common 3-state output enable input\n• Inputs accept voltages higher than VCC\n• Input l;

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Octal D-type transparant latch; 3-state

The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.\n The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuring separate D-type inputs for each latch a • Balanced propagation delays\n• All inputs have a Schmitt trigger action\n• Common 3-state output enable input\n• Functionally identical to the 74AHC373; 74AHCT373\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC573: CMOS input level\n• For 74AHCT573: TTL input level\n\n• ESD p;

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