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74AHCT32PW

Quad 2-input OR gate

DESCRIPTION The 74AHC/AHCT32 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT32 provides the 2-input OR function. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exc

文件:74.4 Kbytes 页数:16 Pages

PHI

飞利浦

PHI

74AHCT32PW

Quad 2-input OR gate

1. General description The 74AHC32; 74AHCT32 is a quad 2-input OR gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits • Wide supply voltage range from 2.0 V to 5.5 V • Input levels: • For 7

文件:228.69 Kbytes 页数:13 Pages

NEXPERIA

安世

74AHCT32PWDH

Quad 2-input OR gate

DESCRIPTION The 74AHC/AHCT32 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT32 provides the 2-input OR function. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exc

文件:74.4 Kbytes 页数:16 Pages

PHI

飞利浦

PHI

74AHCT32PW-Q100

Quad 2-input OR gate

General description The 74AHC32-Q100; 74AHCT32-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC32-Q100; 74AHCT32-Q100 provides the 2-input OR function. This product has been q

文件:705.34 Kbytes 页数:15 Pages

NEXPERIA

安世

74AHCT32PW

Quad 2-input OR gate

The 74AHC32; 74AHCT32 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC32; 74AHCT32 provides the 2-input OR function. • Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC32: CMOS level\n• For 74AHCT32: TTL level\n\n• ESD protection:• HBM EIA/JESD22-A114E exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n• CDM EIA/JESD22-C1;

Nexperia

安世

74AHCT32PW-Q100

Quad 2-input OR gate

The 74AHC32-Q100; 74AHCT32-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC32-Q100; 74AHCT32-Q100 provides the 2-input OR function.\n This product has been qualified to the • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC32-Q100: CMOS level\n•;

Nexperia

安世

74AHCT32PW,112

Package:14-TSSOP(0.173",4.40mm 宽);包装:管件 类别:集成电路(IC) 门和反相器 描述:IC GATE OR 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

74AHCT32PW,118

Package:14-TSSOP(0.173",4.40mm 宽);包装:管件 类别:集成电路(IC) 门和反相器 描述:IC GATE OR 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

74AHCT32PW-Q100J

Package:14-TSSOP(0.173",4.40mm 宽);包装:卷带(TR) 类别:集成电路(IC) 门和反相器 描述:IC GATE OR 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

技术参数

  • VCC (V):

    4.5 - 5.5

  • Logic switching levels:

    TTL

  • Output drive capability (mA):

    ± 8

  • tpd (ns):

    5.0

  • fmax (MHz):

    60

  • Nr of bits:

    4

  • Power dissipation considerations:

    low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    138

  • Ψth(j-top) (K/W):

    6.9

  • Rth(j-c) (K/W):

    64

  • Package name:

    TSSOP14

供应商型号品牌批号封装库存备注价格
NEXPERIA/安世
25+
SOT402-1
600000
NEXPERIA/安世全新特价74AHCT32PW即刻询购立享优惠#长期有排单订
询价
恩XP
24+
TSSOP
3580
原装现货/15年行业经验欢迎询价
询价
PHI
2021+
TSSOP-14
9000
原装现货,随时欢迎询价
询价
PHI
24+
TSSOP14
30000
询价
恩XP
17+
TSSOP
6200
100%原装正品现货
询价
PHI
1999
TSSOP
4780
原装现货海量库存欢迎咨询
询价
PHI
23+
NA
462
专业电子元器件供应链正迈科技特价代理特价,原装元器件供应,支持开发样品
询价
PHI
25+23+
SSOP-14
30120
绝对原装正品全新进口深圳现货
询价
TI
19+
TSSOP
32000
原装正品,现货特价
询价
PHI
ROHS+Original
NA
462
专业电子元器件供应链/QQ 350053121 /正纳电子
询价
更多74AHCT32PW供应商 更新时间2025-12-12 14:13:00