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74AHCT132PW

Quad 2-input NAND Schmitt trigger

DESCRIPTION The 74AHC/AHCT132 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of tr

文件:106.13 Kbytes 页数:16 Pages

PHI

飞利浦

PHI

74AHCT132PW

Quad 2-input NAND Schmitt trigger

1. General description The 74AHC132; 74AHCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits • Wide supply voltage range from 2.0 V t

文件:276.99 Kbytes 页数:16 Pages

NEXPERIA

安世

74AHCT132PWDH

Quad 2-input NAND Schmitt trigger

DESCRIPTION The 74AHC/AHCT132 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of tr

文件:106.13 Kbytes 页数:16 Pages

PHI

飞利浦

PHI

74AHCT132PW-Q100

Quad 2-input NAND Schmitt trigger

文件:744.39 Kbytes 页数:18 Pages

NEXPERIA

安世

74AHCT132PW

Quad 2-input NAND Schmitt trigger

The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC132; 74AHCT132 contains four 2-input NAND gates which accept standard input signals. They are capable of tra • Balanced propagation delays\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC132: CMOS level\n• For 74AHCT132: TTL level\n\n• ESD protection:• HBM EIA/JESD22-A114E exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n• CDM EIA/JESD22-C101C exceeds 1000 V\n\n• Multiple package ;

Nexperia

安世

74AHCT132PW-Q100

Quad 2-input NAND Schmitt trigger

The 74AHC132-Q100; 74AHCT132-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC132-Q100; 74AHCT132-Q100 contains four 2‑input NAND gates which accept standard input signals. The • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Balanced propagation delays\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC132-Q100: CMOS level\n• For 74AHCT132-Q100: TTL level\n\n• ESD protec;

Nexperia

安世

74AHCT132PW,112

Package:14-TSSOP(0.173",4.40mm 宽);包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 类别:集成电路(IC) 门和反相器 描述:IC GATE NAND 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

74AHCT132PW,118

Package:14-TSSOP(0.173",4.40mm 宽);包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 类别:集成电路(IC) 门和反相器 描述:IC GATE NAND 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

74AHCT132PW-Q100J

Package:14-TSSOP(0.173",4.40mm 宽);包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 类别:集成电路(IC) 门和反相器 描述:IC GATE NAND 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

技术参数

  • VCC (V):

    4.5 - 5.5

  • Logic switching levels:

    TTL

  • Output drive capability (mA):

    ± 8

  • tpd (ns):

    3.5

  • fmax (MHz):

    60

  • Nr of bits:

    4

  • Power dissipation considerations:

    low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    138

  • Ψth(j-top) (K/W):

    6.9

  • Rth(j-c) (K/W):

    64

  • Package name:

    TSSOP14

供应商型号品牌批号封装库存备注价格
Nexperia(安世)
24+
TSSOP14
977
只做原装,提供一站式配单服务,代工代料。BOM配单
询价
NEXPERIA
22+
原厂
32000
询价
恩XP
2447
TSSOP14
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
询价
恩XP
21+
TSSOP14
2500
询价
Nexperia(安世)
2021+
TSSOP-14
597
询价
恩XP
24+
TSSOP14
9600
原装现货,优势供应,支持实单!
询价
恩XP
23+
NA
20094
正纳10年以上分销经验原装进口正品做服务做口碑有支持
询价
恩XP
24+
TSSOP-5
30000
原装正品公司现货,假一赔十!
询价
NEXPERIA/安世
2022+
2500
6600
只做原装,假一罚十,长期供货。
询价
恩XP
21+
TSSOP-5
8080
只做原装,质量保证
询价
更多74AHCT132PW供应商 更新时间2025-12-13 8:12:00