Quad 2-input NOR gate

DESCRIPTION The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT02 provides the Quad 2-input OR function. FEATURES • ESD protection: HBM EIA/JESD22-A114-

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PHI

飞利浦

Quad 2-input NOR gate

General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74AHC02; 74AHCT02 provides the quad 2-input NOR function. Features ■ Balanced propagation d

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恩XP

Quad 2-input NOR gate

1. General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. 2. Features and benefits • Balance

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NEXPERIA

安世

Quad 2-input NOR gate

DESCRIPTION The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT02 provides the Quad 2-input OR function. FEATURES • ESD protection: HBM EIA/JESD22-A114-

文件：74.48 Kbytes 页数：16 Pages

PHI

飞利浦

Automotive product qualification in accordance with AEC-Q100

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NEXPERIA

安世

Quad 2-input NOR gate

The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. • Balanced propagation delays\n• All inputs have a Schmitt-trigger action\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC02: CMOS level\n• For 74AHCT02: TTL level\n\n• ESD protection:• HBM EIA/JESD22-A114E exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n• CDM EIA/JESD22-C;

Nexperia

安世

Quad 2-input NOR gate

The 74AHC02-Q100; 74AHCT02-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC02-Q100; 74AHCT02-Q100 provides a quad 2-input NOR function.\n This product has been qualified to • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Balanced propagation delays\n• All inputs have a Schmitt-trigger action\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC02-Q100: CMOS level\n• Fo;

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安世

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE NOR 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE NOR 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 门和反相器 描述：IC GATE NOR 4CH 2-INP 14TSSOP

Nexperia USA Inc.