Quad 2-input NAND gate

DESCRIPTION The 74AHC/AHCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT00 provides the 2-input NAND function. FEATURES • ESD protection: HBM EIA/J

文件：74.06 Kbytes 页数：16 Pages

PHI

PHI

Quad 2-input NAND gate

General description The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74AHC00; 74AHCT00 provides the quad 2-input NAND function. Features ■ Balanced pr

文件：84.6 Kbytes 页数：13 Pages

恩XP

Quad 2-input NAND gate

1. General description The 74AHC00; 74AHCT00 are quad 2-input NAND gates. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features • Wide supply voltage range from 2.0 V to 5.5 V • Input levels: • For 74AHC00: CMO

文件：227.06 Kbytes 页数：12 Pages

NEXPERIA

安世

Quad 2-input NAND gate

DESCRIPTION The 74AHC/AHCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT00 provides the 2-input NAND function. FEATURES • ESD protection: HBM EIA/J

文件：74.06 Kbytes 页数：16 Pages

PHI

PHI

Quad 2-input NAND gate

文件：704.61 Kbytes 页数：15 Pages

NEXPERIA

安世

Quad 2-input NAND gate

The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. JESD7-A.\n The 74AHC00; 74AHCT00 provides the quad 2-input NAND function. • Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC00: CMOS level\n• For 74AHCT00: TTL level\n\n• ESD protection:• HBM EIA/JESD22-A114E exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n• CDM EIA/JESD22-C1;

Nexperia

安世

Quad 2-input NAND gate

The 74HC00-Q100; 74HCT00-Q100 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Input levels:• For 74AHC00-Q100: CMOS level\n• For 74AHCT00-Q100: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• MIL-STD-883, method 3015 ;

Nexperia

安世

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE NAND 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：管件 类别：集成电路（IC） 门和反相器 描述：IC GATE NAND 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 门和反相器 描述：IC GATE NAND 4CH 2-INP 14TSSOP

Nexperia USA Inc.