Quad 2-input EXCLUSIVE-OR gate

DESCRIPTION The 74AHC/AHCT86 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT86 provides the 2-input EXCLUSIVE-OR function. FEATURES • ESD protection: HBM EIA/JESD22-

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PHI

飞利浦

Quad 2-input EXCLUSIVE-OR gate

General description The 74AHC86; 74AHCT86 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC86; 74AHCT86 provides a 2-input exclusive-OR function. Features ■ Balanced propagation

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恩XP

Quad 2-input EXCLUSIVE-OR gate

1. General description The 74AHC86; 74AHCT86 is a quad 2-input EXCLUSIVE-OR gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits • Wide supply voltage range from 2.0 V to 5.5 V • Input levels

文件：235.98 Kbytes 页数：14 Pages

NEXPERIA

安世

Quad 2-input EXCLUSIVE-OR gate

DESCRIPTION The 74AHC/AHCT86 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT86 provides the 2-input EXCLUSIVE-OR function. FEATURES • ESD protection: HBM EIA/JESD22-

文件：75.3 Kbytes 页数：16 Pages

PHI

飞利浦

Automotive product qualification in accordance with AEC-Q100

文件：705.31 Kbytes 页数：15 Pages

NEXPERIA

安世

Quad 2-input EXCLUSIVE-OR gate

The 74AHC86; 74AHCT86 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.\n The 74AHC86; 74AHCT86 provides a 2-input exclusive-OR function. • Balanced propagation delays\n• All inputs have a Schmitt-trigger action\n• Inputs accepts voltages higher than VCC\n• For 74AHC86 only: operates with CMOS input levels\n• For 74AHCT86 only: operates with TTL input levels\n• ESD protection:• HBM JESD22-A114E exceeds 2000 V\n• MM JESD22-A115-A excee;

Nexperia

安世

Quad 2-input EXCLUSIVE-OR gate

The 74AHC86-Q100; 74AHCT86-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.\n The 74AHC86-Q100; 74AHCT86-Q100 provides a 2-input exclusive-OR function.\n This product has been quali • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have a Schmitt-trigger action\n• Inputs accept voltages higher than VCC\n• For 74AHC86-Q100 only: operates with CMOS inp;

Nexperia

安世

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 门和反相器 描述：IC GATE XOR 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 门和反相器 描述：IC GATE XOR 4CH 2-INP 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 门和反相器 描述：IC GATE XOR 4CH 2-INP 14TSSOP

Nexperia USA Inc.