74AHC74PW

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The74AHC/AHCT74arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardNo.7A. FEATURES •ESDprotection: HBMEIA/JESD22-A114-Aexceeds2000V MMEIA/JESD22-A115-Aexceeds200V

PHI

74AHC74PW

Dual D-type flip-flop with set and reset; positive-edge trigger

Generaldescription The74AHC74;74AHCT74isahigh-speedSi-gateCMOSdeviceandispincompatiblewithLow-PowerSchottkyTTL(LSTTL).ItisspecifiedincompliancewithJEDECstandardNo.7-A. Features ■Balancedpropagationdelays ■AllinputshaveSchmitt-triggeractions ■Inputsaccept

ETC

74AHC74PW

Dual D-type flip-flop with set and reset; positive-edge trigger

1.Generaldescription The74AHC74;74AHCT74isahigh-speedSi-gateCMOSdeviceandispincompatiblewith Low-PowerSchottkyTTL(LSTTL).ItisspecifiedincompliancewithJEDECstandardNo.7-A. The74AHC74;74AHCT74isadualpositive-edgetriggered,D-typeflip-flopwithindividualdata

74AHC74PW

Dual D-type flip-flop with set and reset; positive-edge trigger; • Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC74: CMOS level\n• For 74AHCT74: TTL level\n\n• ESD protection:• HBM EIA/JESD22-A114E exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n• CDM EIA/JESD22-C101C exceeds 1000 V\n\n• Multiple package options\n• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q).\n The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation.\n Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.\n

74AHC74PWDH

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The74AHC/AHCT74arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardNo.7A. FEATURES •ESDprotection: HBMEIA/JESD22-A114-Aexceeds2000V MMEIA/JESD22-A115-Aexceeds200V

PHI

74AHC74PW-Q100

Dual D-type flip-flop with set and reset positive-edge trigger

Generaldescription The74AHC74-Q100;74AHCT74-Q100isahigh-speedSi-gateCMOSdeviceandispincompatiblewithLow-PowerSchottkyTTL(LSTTL).ItisspecifiedincompliancewithJEDECstandardNo.7-A. Featuresandbenefits ■AutomotiveproductqualificationinaccordancewithAEC-Q100(Gra

74AHC74PW-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger; • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC74-Q100: CMOS level\n• For 74AHCT74-Q100: TTL level\n\n• ESD protection:• MIL-STD-883, method 3015 exceeds 2000 V\n• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n• Multiple package options\n;

The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q).\n The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation.\n Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74AHC74PW,112

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP

ETC

74AHC74PW,118

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP

ETC

74AHC74PW-Q100J

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 功能：设置（预设）和复位 类别：集成电路（IC） 触发器 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP

ETC