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型号	下载订购	功能描述	制造商上传企业	LOGO
74AHC74	文件：92.28 Kbytes Page：20 Pages	Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V 文件：92.28 Kbytes 页数：20 Pages	PHI PHI	PHI
74AHC74	文件：256.18 Kbytes Page：15 Pages	Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data 文件：256.18 Kbytes 页数：15 Pages	NEXPERIA 安世	NEXPERIA
74AHC74_08	文件：110.24 Kbytes Page：18 Pages	Dual D-type flip-flop with set and reset; positive-edge trigger General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. Features ■ Balanced propagation delays ■ All inputs have Schmitt-trigger actions ■ Inputs accept 文件：110.24 Kbytes 页数：18 Pages	恩XP	恩XP
74AHC74BQ	文件：110.24 Kbytes Page：18 Pages	Dual D-type flip-flop with set and reset; positive-edge trigger General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. Features ■ Balanced propagation delays ■ All inputs have Schmitt-trigger actions ■ Inputs accept 文件：110.24 Kbytes 页数：18 Pages	恩XP	恩XP
74AHC74BQ	文件：256.18 Kbytes Page：15 Pages	Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data 文件：256.18 Kbytes 页数：15 Pages	NEXPERIA 安世	NEXPERIA
74AHC74BQ-Q100	文件：752.8 Kbytes Page：19 Pages	Dual D-type flip-flop with set and reset positive-edge trigger General description The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. Features and benefits ■ Automotive product qualification in accordance with AEC-Q100 (Gra 文件：752.8 Kbytes 页数：19 Pages	NEXPERIA 安世	NEXPERIA
74AHC74D	文件：256.18 Kbytes Page：15 Pages	Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data 文件：256.18 Kbytes 页数：15 Pages	NEXPERIA 安世	NEXPERIA
74AHC74D	文件：110.24 Kbytes Page：18 Pages	Dual D-type flip-flop with set and reset; positive-edge trigger General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. Features ■ Balanced propagation delays ■ All inputs have Schmitt-trigger actions ■ Inputs accept 文件：110.24 Kbytes 页数：18 Pages	恩XP	恩XP
74AHC74D	文件：92.28 Kbytes Page：20 Pages	Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V 文件：92.28 Kbytes 页数：20 Pages	PHI PHI	PHI
74AHC74D-Q100	文件：752.8 Kbytes Page：19 Pages	Dual D-type flip-flop with set and reset positive-edge trigger General description The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. Features and benefits ■ Automotive product qualification in accordance with AEC-Q100 (Gra 文件：752.8 Kbytes 页数：19 Pages	NEXPERIA 安世	NEXPERIA

技术参数

VCC (V)：
2.0 - 5.5
Logic switching levels：
CMOS
Output drive capability (mA)：
± 8
tpd (ns)：
3.7
fmax (MHz)：
170
Power dissipation considerations：
low
Tamb (°C)：
-40~125
Rth(j-a) (K/W)：
106
Ψth(j-top) (K/W)：
20.9
Rth(j-c) (K/W)：
74
Package name：
DHVQFN14

供应商	型号	品牌	批号	封装	库存	备注	价格
芯有半导体（深圳）有限公司	74AHC74	TI	98+	SOP3.9MM	3300	全新原装绝对自己公司现货特价!	询价
深圳市一线半导体有限公司	74AHC74	TI	24+	SOP	200		询价
深圳市豪迈兴电子有限公司	74AHC74	PHI	2602+	TSSOP14	25843	公司原厂原装现货假一罚十!特价出售!强势库存!	询价
深圳市福安瓯科技有限公司	74AHC74	PHI	25+	TSSOP14	450	⊙⊙新加坡大量现货库存,深圳常备现货!欢迎查询!⊙	询价
深圳市佳鑫美电子科技有限公司	74AHC74	PHI	25+	TSSOP14	2987	只售原装自家现货!诚信经营!欢迎来电!	询价
千层芯半导体(深圳)有限公司	74AHC74	Nexperia	24+	SO-14	30000	一级代理进口原装现货假一赔十	询价
深圳市威雅利发展有限公司	74AHC74	TI	25+	TSSOP-14	8000	原厂原包装,终端BOM表可配单	询价
深圳市勤思达科技有限公司	74AHC74PW,118	恩XP	09+	TSSOP14	5500	原装无铅,优势热卖	询价
深圳市凌旭科技有限公司	74AHC74PW	恩XP	2016+	TSOP	2600	只做原装,假一罚十,公司可开17%增值税发票!	询价
深圳市粤科源兴科技有限公司	74AHC74PW	恩XP	13+	TSSOP14	6877	原装分销	询价

更多74AHC74供应商更新时间2026-10-9 15:56:00

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