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74AHC138PW

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A

文件:84.13 Kbytes 页数:16 Pages

PHI

PHI

PHI

74AHC138PW

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary we

文件:260.86 Kbytes 页数:15 Pages

NEXPERIA

安世

74AHC138PWDH

3-to-8 line decoder/demultiplexer; inverting

DESCRIPTION The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A

文件:84.13 Kbytes 页数:16 Pages

PHI

PHI

PHI

74AHC138PW-Q100

Automotive product qualification in accordance with AEC-Q100

文件:718.24 Kbytes 页数:17 Pages

NEXPERIA

安世

74AHC138PW

3-to-8 line decoder/demultiplexer; inverting

The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.\n The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A • Balanced propagation delays\n• All inputs have Schmitt-trigger action\n• Demultiplexing capability\n• Multiple input enable for easy expansion\n• Ideal for memory chip select decoding\n• Inputs accepts voltages higher than VCC\n• For 74AHC138 only: operates with CMOS input levels\n• For 74AHCT138 ;

Nexperia

安世

74AHC138PW-Q100

3-to-8 line decoder/demultiplexer; inverting

The 74AHC138-Q100; 74AHCT138-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.\n The 74AHC138-Q100; 74AHCT138-Q100 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weight • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have Schmitt-trigger action\n• Demultiplexing capability\n• Multiple input enable for easy expansion\n• Ideal for memory;

Nexperia

安世

74AHC138PW,112

Package:16-TSSOP(0.173",4.40mm 宽);包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 类别:集成电路(IC) 信号开关,多路复用器,解码器 描述:IC DECODER/DEMUX 1X3:8 16TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

74AHC138PW,118

Package:16-TSSOP(0.173",4.40mm 宽);包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 类别:集成电路(IC) 信号开关,多路复用器,解码器 描述:IC DECODER/DEMUX 1X3:8 16TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

74AHC138PW-Q100J

Package:16-TSSOP(0.173",4.40mm 宽);包装:卷带(TR) 类别:集成电路(IC) 信号开关,多路复用器,解码器 描述:IC DECODER/DEMUX 1X3:8 16TSSOP

Nexperia USA Inc.

Nexperia USA Inc.

技术参数

  • VCC (V):

    2.0 - 5.5

  • Logic switching levels:

    CMOS

  • Output drive capability (mA):

    ± 8

  • tpd (ns):

    4.4

  • Power dissipation considerations:

    low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    125

  • Ψth(j-top) (K/W):

    4.6

  • Rth(j-c) (K/W):

    54.7

  • Package name:

    TSSOP16

供应商型号品牌批号封装库存备注价格
NEXPERIA/安世
25+
SOT403-1
600000
NEXPERIA/安世全新特价74AHC138PW即刻询购立享优惠#长期有排单订
询价
恩XP
2021+
TSSOP
9000
原装现货,随时欢迎询价
询价
恩XP
18+
NA
2500
询价
ph
24+
N/A
6980
原装现货,可开13%税票
询价
PHI
24+
TSSOP16
35
询价
PHI
25+
TSSOP16
6500
百分百原装正品 真实公司现货库存 本公司只做原装 可
询价
恩XP
24+
SMD
20000
一级代理原装现货假一罚十
询价
恩XP
23+
SSOP16
8650
受权代理!全新原装现货特价热卖!
询价
恩XP
24+
TSSOP
15000
大批量供应优势库存热卖
询价
PHI
25+
TSSOP16
15000
现货
询价
更多74AHC138PW供应商 更新时间2026-1-30 11:47:00