Quad buffer/line driver; 3-state

DESCRIPTION The 74AHC/AHCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT125 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) a

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PHI

PHI

Quad buffer/line driver; 3-state

General description The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A. The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. T

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恩XP

Quad buffer/line driver; 3-state

1. General description The 74AHC125; 74AHCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as

文件：250.5 Kbytes 页数：15 Pages

NEXPERIA

安世

Quad buffer/line driver; 3-state

DESCRIPTION The 74AHC/AHCT125 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT125 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) a

文件：78.87 Kbytes 页数：16 Pages

PHI

PHI

Quad buffer/line driver; 3-state

文件：822.7 Kbytes 页数：17 Pages

NEXPERIA

安世

Quad buffer/line driver; 3-state

The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A.\n The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs • Balanced propagation delays\n• All inputs have a Schmitt-trigger action\n• Inputs accepts voltages higher than VCC\n• For 74AHC125 only: operates with CMOS input levels\n• For 74AHCT125 only: operates with TTL input levels\n• ESD protection:• HBM JESD22-A114E exceeds 2000 V\n• MM JESD22-A115-A exc;

Nexperia

安世

Quad buffer/line driver; 3-state

The 74AHC125-Q100; 74AHCT125-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard JESD7-A.\n The 74AHC125-Q100; 74AHCT125-Q100 provides four non-inverting buffer/line drivers with 3-state outputs. • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have a Schmitt trigger action\n• Inputs accept voltages higher than VCC\n• For 74AHC125-Q100: CMOS input levels\n• For 7;

Nexperia

安世

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUF NON-INVERT 5.5V 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUF NON-INVERT 5.5V 14TSSOP

Nexperia USA Inc.

Package：14-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 缓冲器，驱动器，接收器，收发器 描述：IC BUF NON-INVERT 5.5V 14TSSOP

Nexperia USA Inc.