Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and i

文件：104.16 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is

文件：114.36 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is

文件：114.36 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is

文件：114.36 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and i

文件：104.16 Kbytes 页数：9 Pages

FAIRCHILD

仙童半导体

Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is

文件：114.36 Kbytes 页数：10 Pages

ONSEMI

安森美半导体

Dual D-Type Positive Edge-Triggered Flip-Flop

文件：111.59 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体

Dual D-Type Positive Edge-Triggered Flip-Flop

文件：111.59 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体

Dual D-Type Positive Edge-Triggered Flip-Flop

文件：111.59 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体

Dual D-Type Positive Edge-Triggered Flip-Flop

文件：111.59 Kbytes 页数：10 Pages

FAIRCHILD

仙童半导体