CMOS SyncFIFO

文件：338.75 Kbytes 页数：16 Pages

IDT

CMOS SyncFIFO

文件：338.75 Kbytes 页数：16 Pages

IDT

CMOS SyncFIFO

文件：338.75 Kbytes 页数：16 Pages

IDT

R/A CARDBUS SINGLE DECK ASSEMBLY

文件：184.3 Kbytes 页数：3 Pages

FCI-CONNECTOR

AC 167 RST/ 2 6-7

文件：125.92 Kbytes 页数：2 Pages

ADELS

AC 167 RST/ 3

文件：135.33 Kbytes 页数：1 Pages

ADELS

AC 167 RST/ 2 7-8

文件：138.35 Kbytes 页数：2 Pages

ADELS

Arista 7220R Series Enterprise WAN Router

文件：1.39997 Mbytes 页数：33 Pages

ARISTA

256 x 9 SyncFIFO, 5.0V

The 72201SyncFIFO™ is a 256 x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be 10 ns read/write cycle time\nRead and Write Clocks can be independent\nDual-Ported zero fall-through time architecture\nEmpty and Full Flags signal FIFO status\nProgrammable Almost-Empty and Almost-Full flags can be set to any depth\nProgrammable Almost-Empty and Almost-Full flags default to Empty+7;

Renesas

瑞萨

256 x 18 SyncFIFO, 5.0V

The 72205 is a 256 x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The r 10 ns read/write cycle time\n Empty and Full flags signal FIFO status\n Easy expandable in depth and width\n Asynchronous or coincident read and write clocks\n Programmable Almost-Empty and Almost-Full flags with default settings\n Half-Full flag capability\n Dual-Port zero fall-through time archite;

Renesas

瑞萨