CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16

• 25ns parallel port access time, 35ns cycle time • 50MHz serial shift frequency • Wide x16 organization offering easy expansion • Low power consumption (50mA typical) • Least/Most Significant Bit first read selected by asserting the FL/DIR pin • Four memory status flags: Empty, Full, Half-F

文件：422.51 Kbytes 页数：12 Pages

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CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16

• 25ns parallel port access time, 35ns cycle time • 50MHz serial shift frequency • Wide x16 organization offering easy expansion • Low power consumption (50mA typical) • Least/Most Significant Bit first read selected by asserting the FL/DIR pin • Four memory status flags: Empty, Full, Half-F

文件：422.51 Kbytes 页数：12 Pages

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