3.3V 256K x 16 Asynchronous Static RAM Center Pwr & Gnd Pinout

The 71V416 3.3V CMOS SRAM is organized as 256K x 16. All bidirectional inputs and outputs of the 71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. JEDEC Center Power / GND pinout for reduced noise.\nEqual access and cycle times\n– Commercial and Industrial: 10/12/15ns\nOne Chip Select plus one Output Enable pin\nBidirectional data inputs and outputs directly\nLVTTL-compatible\nLow power consumption via chip deselect\nUpper and Lower Byte Enabl;

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3.3V CMOS Static RAM

文件：645.53 Kbytes 页数：9 Pages

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3.3V CMOS Static RAM

文件：645.53 Kbytes 页数：9 Pages

IDT

3.3V CMOS Static RAM

文件：645.53 Kbytes 页数：9 Pages

IDT

3.3V CMOS Static RAM

文件：645.53 Kbytes 页数：9 Pages

IDT

3.3V CMOS Static RAM

文件：645.53 Kbytes 页数：9 Pages

IDT

3.3V CMOS Static RAM

文件：645.53 Kbytes 页数：9 Pages

IDT

3.3V CMOS Static RAM

文件：645.53 Kbytes 页数：9 Pages

IDT

3.3V CMOS Static RAM

文件：645.53 Kbytes 页数：9 Pages

IDT

3.3V CMOS Static RAM

文件：645.53 Kbytes 页数：9 Pages

IDT