型号：5962-8999001EA；Package：CDIP；High-Speed CMOS Logic Digital Phase-Locked Loop

Features • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically V

文件：318.06 Kbytes 页数：16 Pages

TI2

德州仪器

型号：CD54HC297F3A；Package：CDIP；High-Speed CMOS Logic Digital Phase-Locked Loop

Features • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically V

文件：318.06 Kbytes 页数：16 Pages

TI2

德州仪器

型号：CD54HC297F3A.A；Package：CDIP；High-Speed CMOS Logic Digital Phase-Locked Loop

Features • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically V

文件：318.06 Kbytes 页数：16 Pages

TI2

德州仪器

型号：5962-8999001EA；Package：CDIP；High-Speed CMOS Logic Digital Phase-Locked Loop

Features • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically V

文件：318.06 Kbytes 页数：16 Pages

TI2

德州仪器

型号：5962-8999001EA；High-Speed CMOS Logic Digital Phase-Locked Loop

文件：251.63 Kbytes 页数：15 Pages

TI1

德州仪器