3.3V Zero Delay Clock Multiplier

The 2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency\n• Separate output enable for each output bank\n• Output Skew <200 ps\n• 1x, 2x, 4x output options: - 2308A-1 1x - 2308A-2 1x, 2x - 2308A-3 2x, 4x - 2308A-4 2x - 2308A-1H and -2H for High Drive\n• ;

Renesas

瑞萨

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK MULT ZD STD DRV 16-SOIC

Renesas Electronics America Inc

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK MULT ZD STD DRV 16-SOIC

Renesas Electronics America Inc

Package：16-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK MULT ZD STD DRV 16-SOIC

Renesas Electronics America Inc