Low Power Single Supply Hex TTL-to-PECL Translator

General Description The 100391 is a hex translator for converting TTL logic levels to F100K PECL logic levels. The unique feature of this translator, is the ability to do this translation using only one +5V supply. The differential outputs allow each circuit to be used as an inverting/non-inverti

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Low Power 9-Bit ECL-to-TTL Translator with Latches

General Description The 100393 is a 9-bit translator for converting F100K logic levels to TTL logic levels. A LOW on the latch enable (LE) latches the data at the input state. A HIGH on the LE makes the latches transparent. A HIGH on either the ECL or TTL output enable (OE ECL or OE TTL), holds t

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Low Power 9-Bit ECL-to-TTL Translator with Latches

General Description The 100393 is a 9-bit translator for converting F100K logic levels to TTL logic levels. A LOW on the latch enable (LE) latches the data at the input state. A HIGH on the LE makes the latches transparent. A HIGH on either the ECL or TTL output enable (OE ECL or OE TTL), holds t

文件：60.91 Kbytes 页数：6 Pages

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Low Power 9-Bit ECL-to-TTL Translator with Registers

General Description The 100395 is a 9-bit translator for converting F100K logic levels to TTL logic levels. A HIGH on the output enable (OE) holds the TTL outputs in a high impedance state. Two separate clock inputs are available for multiplexing and system level testing. The 100395 is designed

文件：54.4 Kbytes 页数：5 Pages

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Low Power 9-Bit ECL-to-TTL Translator with Registers

General Description The 100395 is a 9-bit translator for converting F100K logic levels to TTL logic levels. A HIGH on the output enable (OE) holds the TTL outputs in a high impedance state. Two separate clock inputs are available for multiplexing and system level testing. The 100395 is designed

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Quad Differential ECL/TTL Translating Transceiver with Latch

General Description The 100397 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. The

文件：129.65 Kbytes 页数：13 Pages

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Quad Differential ECL/TTL Translating Transceiver with Latch

General Description The 100397 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. The

文件：129.65 Kbytes 页数：13 Pages

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Quad Differential ECL/TTL Translating Transceiver with Latch

General Description The 100397 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. The

文件：129.65 Kbytes 页数：13 Pages

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Quad Differential ECL/TTL Translating Transceiver with Latch

General Description The 100397 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. The

文件：129.65 Kbytes 页数：13 Pages

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Quad Differential ECL/TTL Translating Transceiver with Latch

General Description The 100398 is a quad latched transceiver designed to convert TTL logic levels to differential F100K ECL logic levels and vice versa. This device was designed with the capability of driving a differential 25Ω ECL load with cutoff capability, and will sink a 64 mA TTL load. Th

文件：117.87 Kbytes 页数：13 Pages

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