ZL30347中文资料Network Synchronization数据手册Microchip规格书

描述 Description

The ZL30347 is a member of a family of footprint-compatible devices offering the full range of features required for timing and synchronization across packet networks.  This device focus on the Clock Recovery, Servo Mechanism and Clock Generation for Synchronization using IEEE-1588.  They work seamlessly with Time Stamp solutions from all the major Switch/PHY NPU/CPU vendors.

This single chip device offers both packet timing using IEEE-1588 Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) capable of driving the physical layer clock with the required very low jitter. The ZL30347 offers a full Stratum 3 DPLL, ideal for Timing Card applications and supports clock recovery over L2 and L3 networks for all wireless applications.

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特性 Features

• Recovers and transmits network synchronization over Ethernet, IP, MPLS networks
• Capable of server, client and Boundary Node operation
• Integrates two separate digital phase locked loops
• Recovers clocks from two independent servers, with hitless switching between packet streams for redundancy
• Hitless switching from Packet to Packet, Packet to Electrical, Electrical to Packet
• Accepts eight input references, and up to three associated low frequency alignment or framing pulses
• Generates up to four separate output clocks at frequencies between 8 kHz and 100 MHz
• Generates two separate Synchronous Ethernet clocks to drive industry standard Ethernet PHY devices at either 25 MHz or 125 MHz
Typical Applications
• Integrated basestation reference clock for air interface for GSM, WCDMA, LTE and WiMAX macro, micro or femtocells
• Mobile Backhaul NID, edge router or access aggregation node
• EPON/GE-PON & GPON OLT
• EPON/GE-PON & GPON ONU/OLT
• DSLAM and RT-DSLAM

简介

ZL30347属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30347应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。