ZL30162中文资料Network Synchronization数据手册Microchip规格书

描述 Description

The ZL30162 is Microsemi's most integrated timing card device combining four programmable DPLLs / NCOs with four programmable synthesizers.  The deivce is a fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion DPLL.  It is capable of accepting or generating any frequency from 1Hz to 750MHz on up to eleven input references and up to sixteen output clocks. 

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特性 Features

• Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion Digital Phase Locked Loop (DPLL)
• Four independent, programmable DPLLs/Numerically Controlled Oscillators (NCOs) synchronize to any clock rate from 1 Hz to 750 MHz
• Four programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.61 ps rms
• Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
• Digital PLLs filter jitter 0.1 mHz up to 1 kHz
• Programmable DPLLs can synchronize to sync pulse and sync pulse/clock pair
• Automatic hitless reference switching and digital holdover on reference fail
• Reference inputs:
• Nine reference inputs configurable as single ended or differential
• Two additional single ended reference inputs
• Any Output Frequency:
• Eight LVPECL output clocks
• Eight LVCMOS output clocks
• Up to four unique customer defined default configurations, including input/output frequencies, are available via OTP (One Time Programmable) memory
• Easy Configuration and dynamic programming via SPI/I2C interface
• Operates from a single crystal resonator or clock oscillator

简介

ZL30162属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30162应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。