ZL30161数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

描述 Description

The ZL30161 is a single channel Network Synchronization Clock Translator combining a single DPLL / NCO with three programmable synthesizers.  The device is a fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion DPLL.  It is capable of accepting and generating any frequency from 1Hz to 750MHz on up to eleven input references and up to twelve output clocks.

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特性 Features

• Fully compliant SEC (G.813), EEC (G.8262) and Stratum 3E flexible rate conversion digital phase locked loop (DPLL)
• Programmable DPLL/Numerically Controlled Oscillators (NCO)
• Synchronizes to any clock rate from 1 Hz to 750 MHz
• Three programmable synthesizers generate any clock rate from 1 Hz to 750 MHz with maximum jitter below 0.62 ps rms
• Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
• Digital PLL filters jitter from 0.1 mHz up to 1 kHz
• Automatic hitless reference switching and digital holdover on reference fail
• Nine input references configurable as single ended or differential and two single ended input references
• Any input reference can be fed with sync (frame pulse) or clock
• Programmable DPLL can synchronize to sync pulse and sync/clock pair.
• Six LVPECL outputs and six LVCMOS outputs
• Operates from a single crystal resonator or clock oscillator
• Customer defined default device configuration available via OTP (One Time Programmable) memory, including input/output frequencies
• Dynamically configurable via SPI/I2C interface and volatile configuration registers

简介

ZL30161属于集成电路（IC）的应用特定时钟/定时。由制造生产的ZL30161应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。