XRT91L34中文资料Quad Channel Multirate STS-12/3/1 and STM-4/1/0 SONET/SDH CDR数据手册MaxLinear规格书

描述 Description

The XRT91L34 is a fully integrated quad channel multirate Clock and Data Recovery (CDR) device for SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/STM-1 or 51.84 Mbps STS-1/STM-0 applications. The device provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The device internally monitors Loss of Lock (LOL) conditions and automatically mutes recovered data upon Loss of Signal (LOS) conditions.
Clock and Data Recovery Overview
The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the LVDS or Differential LVPECL receiver and generates a clock that is the same frequency as the incoming data. The CDR block uses a reference clock to train and monitor its clock recovery PLL. All four channels share a single 77.76MHz or 19.44MHz reference clock. Upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL attempts to lock onto the incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock back onto the local reference clock and declare a Loss of Lock.
Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will continue to supply a recovered clock (based on the local reference) to the framer/mapper device. When the SDEXT is de-asserted by the optical module or when internal DLOS is asserted, the receive serial data output will be forced to a logic zero state for the entire duration that a LOS condition is declared. This acts as a receive data mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When the SDEXT becomes active and the recovered clock is determined to be within ±500 ppm accuracy with respect to the local reference source and LOS is no longer declared, the clock recovery PLL will switch and lock back onto the incoming receive serial data stream.

特性 Features

·Quad Channel CDR targeted for SONET STS-12/STS-3/STS-1 and SDH STM-4/STM-1/STM-0 Applications
·Selectable data rate operation between 622.08 Mbps, 155.52 Mbps, or 51.84 Mbps
·Single-chip fully integrated solution containing quad-channel clock and data recovery (CDR) functions
·Optional flexibility to configure for LVDS or Differential LVPECL High Speed I/O Interface
·Internal 100W termination for the high speed LVDS/Differential LVPECL inputs included
·Utilizes reference clock frequency of either 19.44 MHz or 77.76 MHz
·Host mode serial microprocessor interface simplifies monitor and control, including LOS monitoring
·Diagnostics features include LOS monitoring in Host Mode and automatic recovered data mute upon LOS
·Loss of Lock Detect output for each channel
·Permits mixed data rate configuration of the four channels
·Independent power down control of unused channels for lower power operation
·Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, and GR-253 CORE, GR-253 ILR SONET Jitter specifications
·Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V Differential LVPECL, and JESD 8-B LVTTL and LVCMOS standard
·Operates with dual power supply of 1.8V core and 3.3V IO supply
·90mW LVDS/ 350mW Differential LVPECL per channel Typical Power Dissipation
·Package: 14 x 14 x 1.4 mm 128-pin LQFP
·RoHS Compliant Lead-Free package availability
·ESD greater than 2kV on all pins

应用 Application

·SONET/SDH-based Transmission Systems·Add/Drop Multiplexers·Cross Connect Equipment·ATM and Multi-Service Switches, Routers and Switch/Routers·DSLAMS·SONET/SDH Test Equipment·DWDM Termination Equipment