W971GG8JB

16M 횞 8 BANKS 횞 8 BIT DDR2 SDRAM

GENERALDESCRIPTION TheW971GG8JBisa1GbitsDDR2SDRAM,organizedas16,777,216wordsx8banksx8bits.Thisdeviceachieveshighspeedtransferratesupto1066Mb/sec/pin(DDR2-1066)forgeneralapplications.W971GG8JBissortedintothefollowingspeedgrades:-18,-25,25I,25A,25Kand-

W971GG8JB

双倍数据传输速率同步动态随机存取内存-2nd generation(第二代); •Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V\n• Double Data Rate architecture: two data transfers per clock cycle \n• CAS Latency: 3, 4, 5, 6 and 7 \n• Burst Length: 4 and 8\n• Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data\n• Edge-aligned with Read data and center-aligned with Write data\n• DLL aligns DQ and DQS transitions with clock \n• Differential clock inputs (CLK and /CLK)\n• Data masks (DM) for write data\n• Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS\n• Posted /CAS programmable additive latency supported to make command and data bus efficiency\n• Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)\n• Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality \n• Auto-precharge operation for read and write bursts \n• Auto Refresh and Self Refresh modes\n• Precharged Power Down and Active Power Down \n• Write Data Mask\n• Write Latency = Read Latency - 1 (WL = RL - 1)\n• Interface: SSTL_18\n• Package:WBGA 60 Ball(8x12.5mm2), RoHS compliant;

The W971GG8JB is a 1G bits DDR2 SDRAM, and speed involving -18, -25, 25I, 25A, 25K and -3.\n

W971GG8JB

16M x 8 BANKS x 8 BIT DDR2 SDRAM

W971GG8JB_12

16M x 8 BANKS x 8 BIT DDR2 SDRAM

W971GG8JB-18

16M x 8 BANKS x 8 BIT DDR2 SDRAM

W971GG8JB-25

16M x 8 BANKS x 8 BIT DDR2 SDRAM

W971GG8JB25A

16M x 8 BANKS x 8 BIT DDR2 SDRAM

W971GG8JB25I

16M x 8 BANKS x 8 BIT DDR2 SDRAM

W971GG8JB25K

16M x 8 BANKS x 8 BIT DDR2 SDRAM

W971GG8JB-3

16M x 8 BANKS x 8 BIT DDR2 SDRAM