W9725G2JB

双倍数据传输速率同步动态随机存取内存-2nd generation(第二代); •Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V \n• Double Data Rate architecture: two data transfers per clock cycle \n• CAS Latency: 3, 4, 5, 6 and 6 \n• Burst Length: 4 and 8 \n• Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data \n• Edge-aligned with Read data and center-aligned with Write data \n• DLL aligns DQ and DQS transitions with clock \n• Differential clock inputs (CLK and /CLK) \n• Data masks (DM) for write data \n• Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS \n• Posted /CAS programmable additive latency supported to make command and data bus efficiency \n• Read Latency = Additive Latency plus CAS Latency (RL = AL + CL) \n• Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality \n• Auto-precharge operation for read and write bursts \n• Auto Refresh and Self Refresh modes \n• Precharged Power Down and Active Power Down \n• Write Data Mask \n• Write Latency = Read Latency - 1 (WL = RL - 1) \n• Interface: SSTL_18\n• Package:TFBGA128 Ball (10.5X13.5 mm2), RoHS compliant;

The W9725G2JB is a 256M bits DDR2 SDRAM, and speed involving -25 and -3\n

W9725G6KB-25

WINBOND
BGA

W972GG6JB-25其他被动元件

WINBOND/华邦
BGA-84

WINBOND/华邦

W9751G6JB-25

WINBOND
FBGA

W9751G6JB-25

WINBOND
WBGA84