W632GU6KB中文资料双倍数据传输速率同步动态随机存取内存-3rd generation(第三代)数据手册Winbond规格书

描述 Description

The W632GU6KB is a 2G bits DDR3L SDRAM and speed involving -11, 11I, -12, 12I, 12J, -15, 15I and 15J

特性 Features

•Power Supply: 1.35 (typ.), VDD, VDDQ = 1.283 V to 1.45 V
• Backward compatible to VDD, VDDQ = 1.5V±0.075V
• Double Data Rate architecture: two data transfers per clock cycle
• Eight internal banks for concurrent operation
• 8 bit prefetch architecture
• CAS Latency: 6, 7, 8, 9, 10, 11 and 13
• Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-The-Fly (OTF)
• Programmable read burst ordering: interleaved or nibble sequential
• Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
• Edge-aligned with read data and center-aligned with write data
• DLL aligns DQ and DQS transitions with clock
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge, data and data mask are referenced to both edges of a differential data strobe pair (double data rate)
• Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command, address and data bus efficiency
• Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
• Auto-precharge operation for read and write bursts
• Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
• Precharged Power Down and Active Power Down
• Data masks (DM) for write data
• Programmable CAS Write Latency (CWL) per operating frequency
• Write Latency WL = AL + CWL
• Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence
• System level timing calibration support via write leveling and MPR read pattern
• ZQ Calibration for output driver and ODT using external reference resistor to ground
• Asynchronous RESET# pin for Power-up initialization sequence and reset function
• Programmable on-die termination (ODT) for data, data mask and differential strobe pairs
• Dynamic ODT mode for improved signal integrity and preselectable termination impedances during writes
• 2 K Byte page size
• Package:WBGA96 Ball (9x13mm2), RoHS compliant