VG36641641BT中文资料世界先进数据手册PDF规格书

描述 Description

The device is CMOS Synchronous Dynamic RAM organized as 1,048,576 - word x 16-bit x 4-bank. it is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.

特性 Features

• Single 3.3V (±0.3V) power supply

• High speed clock cycle time : 8/10ns

• Fully synchronous with all signals referenced to a positive clock edge

• Programmable CAS Iatency (2,3)

• Programmable burst length (1,2,4,8,&Full page)

• Programmable wrap sequence (Sequential/Interleave)

• Automatic precharge and controlled precharge

• Auto refresh and self refresh modes

• Quad Internal banks controlled by A12 & A13 (Bank select)

• Each Bank can operate simultaneously and independently

• LVTTL compatible I/O interface

• Random column access in every cycle

• X16 organization

• Input/Output controlled by LDQM and UDQM

• 4,096 refresh cycles/64ms

• Burst termination by burst stop and precharge command

• Burst read/single write option