VG3617161DT-10中文资料世界先进数据手册PDF规格书

描述 Description

The VG3617161DT is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V power supply. This SDRAM is delicately designed with performance concern for current high-speed application. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II.

特性 Features

• Single 3.3V +/- 0.3V power supply

• Clock Frequency: 180MHz, 166MHz, 143MHz, 125MHz, 100MHz

• Fully synchronous with all signals referenced to a positive clock edge

• Programmable CAS Iatency (2,3)

• Programmable burst length (1,2,4,8,& Full page)

• Programmable wrap sequence (Sequential/Interleave)

• Automatic precharge and controlled precharge

• Auto refresh and self refresh modes

• Dual internal banks controlled by A11(Bank select)

• Simultaneous and independent two bank operation

• I/O level : LVTTL interface

• Random column access in every cycle

• X16 organization

• Byte control by LDQM and UDQM

• 4096 refresh cycles/64ms

• Burst termination by burst stop and precharge command