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V62/24630-01XE中文资料德州仪器数据手册PDF规格书

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厂商型号

V62/24630-01XE

功能描述

LMX1860-SEP Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider

丝印标识

LMX1860

封装外壳

HTQFP

文件大小

2.98315 Mbytes

页面数量

64

生产厂商

TI

中文名称

德州仪器

网址

网址

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-10-10 13:37:00

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V62/24630-01XE价格和库存,欢迎联系客服免费人工找货

V62/24630-01XE规格书详情

1 Features

• VID #V62/24630

– Total ionizing dose 30krad (ELDRS-free)

– Single event latch-up (SEL) immune up to

43MeV - cm2 /mg

– Single event functional interrupt (SEFI) immune

up to 43MeV - cm2 /mg

• Clock buffer for 300MHz to 15GHz frequency

• Ultra-Low Noise

– Noise floor of –159dBc/Hz at 6GHz output

– 36-fs additive jitter (100Hz to fCLK) at 6GHz

output

– 5fs additive jitter (100Hz - 100MHz)

• 4 high-frequency clocks with corresponding

SYSREF outputs

– Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and

8

– Shared programmable multiplier x2, x3, and x4

• Support pin mode options to configure the device

without SPI

• LOGICLK output with corresponding SYSREF

output

– On separate divide bank

– 1, 2, 4 pre-divider

– 1 (bypass), 2, …, 1023 post divider

• 8 programmable output power levels

• Synchronized SYSREF clock outputs

– 508 delay step adjustments of less than 2.5ps

each at 12.8GHz

– Generator and repeater modes

– Windowing feature for SYSREFREQ pins to

optimize timing

• SYNC feature to all divides and multiple devices

• 2.5V operating voltage

• –55ºC to 125ºC operating temperature

• High Reliability

– Controlled Baseline

– One Assembly/Test Site

– One Fabrication Site

– Extended Product Life Cycle

– Product Traceability

2 Applications

• Radar imaging payload

• Communications payloads

• Command and data handling

• Data converter clocking

• Clock distribution/multiplication/division

3 Description

The LMX1860-SEP is an buffer, divider and multiplier

that features high frequency, ultra-low jitter, and

SYSREF outputs. This device combined with an ultralow

noise reference clock source is an exemplary

design for clocking data converters, especially when

sampling above 3GHz. Each of the 4 high frequency

clock outputs and additional LOGICLK output is

paired with a SYSREF output clock signal. The

SYSREF signal for JESD interfaces can either be

internally generated or passed in as an input and

re-clocked to the device clocks. This device can

distribute the multichannel, low skew, ultra-low noise

local oscillator signals to multiple mixers by disabling

the SYSREF outputs.

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TI
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