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V62/24618-01XE中文资料德州仪器数据手册PDF规格书

V62/24618-01XE
厂商型号

V62/24618-01XE

功能描述

SN54SC6T14-SEP Radiation Tolerant, Hex Schmitt-Trigger Inverters With Integrated Translation

丝印标识

SC14SEP

封装外壳

TSSOP

文件大小

1.01832 Mbytes

页面数量

24

生产厂商 Texas Instruments
企业简称

TI1德州仪器

中文名称

美国德州仪器公司官网

原厂标识
数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-6-29 23:00:00

人工找货

V62/24618-01XE价格和库存,欢迎联系客服免费人工找货

V62/24618-01XE规格书详情

1 Features

• Vendor item drawing available, VID V62/24618

• Total ionizing dose characterized at 30 krad (Si)

– Total ionizing dose radiation lot acceptance

testing (TID RLAT) for every wafer lot to 30

krad (Si)

• Single-event effects (SEE) characterized:

– Single event latch-up (SEL) immune to linear

energy transfer (LET) = 43 MeV-cm2 /mg

– Single event transient (SET) characterized to

43 MeV-cm2 /mg

• Wide operating range of 1.2V to 5.5V

• Single-supply translating gates at

5/3.3/2.5/1.8/1.2V VCC

– TTL compatible inputs:

• Up translation:

– 1.8-V – Inputs from 1.2V

– 2.5V – Inputs from 1.8V

– 3.3V – Inputs from 1.8V, 2.5V

– 5.0V – Inputs from 2.5V, 3.3V

• Down translation:

– 1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V

– 1.8-V – Inputs from 2.5V, 3.3V, 5.0V

– 2.5V – Inputs from 3.3V, 5.0V

– 3.3V – Inputs from 5.0V

• 5.5V tolerant input pins

• Output drive up to 25 mA AT 5V

• Latch-up performance exceeds 250 mA per

JESD 17

• Space enhanced plastic (SEP)

– Controlled baseline

– Gold bondwire

– NiPdAu lead finish

– One assembly and test site

– One fabrication site

– Military (–55°C to 125°C) temperature range

– Extended product life cycle

– Product traceability

– Meets NASAs ASTM E595 outgassing

specification

2 Applications

• Enable or disable a digital signal

• Controlling an indicator LED

• Translation between communication modules and

system controllers

3 Description

The SN54SC6T14-SEP device contains six

independent Inverters with Schmitt-trigger inputs

and extended voltage operation to allow for level

translation. Each gate performs the Boolean function

Y = A in positive logic. The output level is referenced

to the supply voltage (VCC) and supports 1.2V, 1.8-V,

2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example 1.2V input to 1.8V output or 1.8V input

to 3.3V output). Additionally, the 5V tolerant input pins

enable down translation (for example 3.3V to 2.5V

output).

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