UPD16780A中文资料瑞萨数据手册PDF规格书

FEATURES

• 5.0 V Drive (Dynamic range 4.6 VP-P, VDD2 = 5.0 V)

• 300 Output channel

• fCLK = 20 MHz MAX. (VDD1 = 3.0 V)

• 1-phase/3-phase sampling clocks supported

• Corresponds only to LCD of Stripe array color filter

• Two on-chip sample-and-hold circuits

• Small output deviation between pins (deviation between chip pins: ±20 mV MAX.)

• Switch between right and left shift using the R,/L pin

• Logic power supply voltage (VDD1): 3.0 to 5.5 V

• Driver power supply voltage(VDD2): 5.0 ± 0.5 V